Location: Bangalore, Karnataka, India
Category: Engineering
Salary: 0 - 0 INR / yearly
Full-time
We are seeking a Lead Physical Design Backend Integration to join our team. The ideal candidate will be responsible for full chip level design, power planning, low power design, synthesis, clock tree implementation, and PPA closure.
Full chip level Die size estimation, Floor-planning, Power planning, IO planning, package compatibility, IO ring creation and ESD analysis.
Full chip Hierarchical planning, block planning, block level constraints, hierarchical clock tree implementation, block integration and chip finishing.
Low power design with power estimation/optimization including clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption.
Full chip/Sub-system/Partition level Synthesis, Logic equivalence, implementation of low power UPF/CPF.
Bachelors or Master's degree in Computer/Electronics/Electrical Engineering.