Location: Pune, Maharashtra, India
Category: Engineering
Salary: 1,500,000 - 2,500,000 INR / yearly
Full-time
Marvell is seeking a Senior Staff Verification Engineer to lead DV efforts for blocks, subsystems, and top-level verification. Join us in empowering the global data economy with innovative technology.
Lead DV efforts for blocks, subsystems, and top-level verification.
Develop and maintain UVM-based verification environments.
Define and review test plans with architecture and design teams.
Verify designs using directed and constrained random techniques.
Maintain regression, debug failures, and analyze coverage.
Drive verification to meet coverage targets.
Contribute to next-gen data processing and hardware accelerator verification.
Focus on networking domain verification for future solutions.
Ensure design closure using innovative and automated techniques.
Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field with 8+ years of professional experience.
Strong experience with Verilog, SystemVerilog, and UVM.
Proficiency in SystemVerilog, C, C++, and scripting languages.
Strong debugging skills and verification flow optimization.
Excellent verbal and written communication skills.
Competitive compensation, great benefits, shared collaboration, transparency, inclusivity.
Tools and resources for success, growth, and development.
Workstyle that matters and fosters personal and professional growth.
Marvell offers purposeful and enduring innovation, empowering individuals and industries.
Thrive, learn, and lead in a transformative environment.