Location: Bengaluru, Karnataka, India
Category: Engineering
Salary: 0 - 0 INR / yearly
Full-time
Cadence is seeking a Principal Design Engineer with extensive experience in design verification. The ideal candidate should have a strong background in functional verification fundamentals, environment planning, and UVM/System Verilog coding.
Lead projects from concept to verification closure
Develop functional verification environments
Generate test plans
Verify complex designs
BE/BTech/ME/MTech in Electrical/Electronics/VLSI
8+ years of Design Verification experience
Experience with SV/UVM
Strong hands-on UVM and System Verilog coding skills
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