ASIC Design Engineer - RTL Design (Verilog/System Verilog) at Hiredas - Bengaluru, Karnataka ASIC Design Engineer - RTL Design (Verilog/System Verilog) - Hiredas

ASIC Design Engineer - RTL Design (Verilog/System Verilog)

Hiredas

Location: Bengaluru, Karnataka, India

Category: Engineering

Salary: 1,000,000 - 1,500,000 INR / yearly

Full-time

Job Description

Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. The team provides a unique experience for ASIC engineers by combining resources from a sizable multi-geography silicon organization with the startup culture and growth opportunities of a smaller ASIC team.

Responsibilities

  • Write micro-architecture specifications and participate in reviews.
  • Implement Verilog RTL to meet timing, performance, and power requirements.
  • Contribute to full chip integration and timing methodology/analysis.
  • Develop and analyze functional coverage.
  • Collaborate with the verification team to address design bugs and close code coverage.
  • Perform diagnostic and post-silicon validation tests in the lab.

Qualifications

  • Bachelor's Degree / Master's Degree in Electrical or Computer Engineering with 7+ years of ASIC design experience.
  • Prior experience working with Verilog or System Verilog programming skills.
  • Experience with simulators, synthesis, static timing constraints, and related tools (e.g., VCS, DC, PrimeTime).
  • Experience with debugging and verification methodologies.

Perks & Benefits

On-site gym, healthcare, cafeteria, social interest groups, philanthropy, learning and development opportunities, paid time off to volunteer.

Why Join Us?

Join us at Cisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.

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